If you want to achieve the ultimate in performance, power consumption and unit price, the ASIC is still king. However, the reality is that the cost and complexity of designing an ASIC has risen dramatically in recent years. Today a mainstream ASIC has mask and tooling costs alone in excess of $1M. To justify such an expense, designs need to be shipping in the tens or even hundreds of thousands to make designing a leading-edge ASIC a viable proposition. Add to this cost the possibility that an ASIC can contain bugs - and require a re-spin with an additional engineering charges and schedule delay, and it becomes obvious the decision to design an ASIC will not be taken lightly. Why incur these costs and risks? Because if your product is going to ship in high volume or needs the absolute peak performance, an ASIC is still the only technology to deliver the unique combination of price, power and performance.

Having said that, there are ways to reduce the up front risk of designing an ASIC. FPGAs are commonly used for this purpose - although this can generate some issues.

FPGA Conversions
One market we see a lot of activity in is the conversion of large, expensive FPGAs into cost-effective ASICs that are pin compatible and have exactly the same functionality. Many semiconductor vendors offer this service and depending on how good business is, they sometimes offer to do the conversion for free (empty semiconductor factories are a very expensive depreciating asset). Our experience is 'caveat emptor' or 'buyer beware'. These programs CAN work very well and CAN dramatically reduce the piece price. However, they can also be a nightmare where the ASIC silicon does not meet the FPGA timing or as soon as the ASIC is received the chip requirements change and it is necessary to go straight back to an FPGA.

Analog and ASICs
There is a whole class of ASICs referred to as "mixed signal" in which a significant amount of the chip is analog. This is a specialized market that Octera doesn't participate in at this time. However, we are often asked to include analog blocks on ASIC designs - typically A/D's, D/As and various types of modulation schemes. Some analog blocks are required for most modern ASIC designs -- for example PLLs to generate different clock frequencies from a common source or SERDES for off-chip communication. These are standard functions that can be included on what is considered a standard digital ASIC. Beyond that, the benefits of custom analog functions must be carefully weighed against the costs. For example, external A/Ds are very inexpensive and very high performance. They CAN be included on the chip and sometimes it is necessary for integration, board space and/or power - but often this is simply a marketing wish that significantly increases the cost of the ASIC without good cause.

Memory and ASICs
Another request that we often encounter is to have large amounts of memory on chip - especially flash memory. Again, it can be done but rarely makes sense. External DDR is very cheap and DDR controller IP is common place. Adding flash memory to an ASIC is very costly and can significantly limit your choice of vendor. In contrast, external flash memory is very inexpensive and unlike onboard flash, the size can easily be increased if you run out of code space.

Types of ASIC vendor
Today ASIC vendors fall into a few distinct categories:

Some own their own fabrication line (fab), help you design the ASIC and then manufacture it for you. Some offer all the elements: process technology, IP and packaging technology - but use a third party's fab. Some offer to pull all the elements together for you from a suitable IP vendor, packaging house and third party fab. And finally, there is the COT (customer own tooling) option whereby the complete frontend and backend design flow is your responsibility but you use a third party fab.

Type of vendor Example Pros and cons
Full service, own fab. IBM, NEC , Toshiba All in one place. Can be expensive. Limits IP and often require high volume. Low risk.
Full service, 3rd party fab. LSI The third party fab. is usually invisible, can be expensive. Low risk.
Full service, COT Open Silicon Hybrid model with medium risk but generally lower piece prices.
COT TSMC, UMC Lowest cost, highest risk, high tool costs, complex engineering

This probably seems bewildering - surely you want to work with a company that controls their own manufacturing? Well, in truth, the cost of building a semiconductor fabrication line is now so high that even IBM uses fab space from third parties and will probably partner up with someone to build the next generation plants. Most companies worldwide use a handful of partners who actually build their chips. The most common ones are TSMC, UMC and Chartered. It's highly likely that one of these companies will be building your chip - the question is: what's the best route to get there? This depends on your project requirements, your appetite for risk vs. cost and the schedule you are working against.

Copyright 2015 Octera Corporation.